1. Field
Embodiments relate to delay locked loops (DLLs) and, more particularly, to a digital DLL including a skewed gate type duty correction circuit and a duty correction method thereof.
2. Description of the Related Art
Typically, a synchronous semiconductor memory device capable of being mounted on a data processing device such as a personal computer, a notebook computer or a portable electronic device adopts a delayed locked loop (hereinafter referred to as “DLL”).
A DLL generates an internal clock signal phase-locked with an external clock signal as an output clock signal to perform an operation of a semiconductor device synchronously with the external clock signal. That is, a DLL may be employed to synchronize an internal clock signal with an external clock signal. More particularly, a timing delay unavoidably occurs when an internally used clock signal passes a block buffer and a transmission line of a semiconductor device, so a DLL can serve as a phase adjuster to synchronize the internal clock signal with the external clock signal.
In case of a semiconductor memory device using an output clock signal generated from a DLL, a signal timing margin may be maximally secured when a duty cycle rate of the output clock signal is maintained at 50 percent. However, the duty ratio of the output clock signal frequently deviates from 50 percent due to characteristics of a jitter outside the DLL and non-uniform delay values of delay elements inside the DLL. Thus, a duty correction circuit may be employed by a DLL to perform a duty correction operation.
Especially, in case of devices that are sensitive to a duty of a clock, like a double data rate (DDR) type semiconductor memory device, it is almost essential that a duty correction circuit (hereinafter referred to as “DCC”) be embedded in a DLL. That is, a data valid window is reduced as a frequency of a clock signal becomes high. In addition, when data is transmitted and received at a dual edge like the DDR-type semiconductor memory device, the data valid window is further reduced. Thus, a duty cycle of a clock signal must be maintained at a ratio of 50:50 to secure a data valid window as widely as possible.